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1) Begin by creating a netlist for SR-Latch. Latch should have two inputs (S and R) and two outputs (Q and QN). Be sure to also include ground and VDD. Make each transistor of your latch minimum-sized (use the minimum width and length for each transistor).

2) Simulate SR-latch to ensure that it works properly (use a transient analysis)–test setting Q to 1, holding this output value, resetting Q to 0, holding this output value, asserting set and reset at the same time, and holding this output value. I suggest that you create a subcircuit (in Spice, this is .SUBCKT) of your latch.

3) Then we need to modify the code to create a fanout-of-4 (FO4) at each output of SR-latch–this is one common way to add load to a circuit in order to more accurately measure its performance. To create a FO4 configuration, use two additional, identical copies of your latch as loads. Connect your Q output to both the S and R inputs of one of your load latches and connect your QN output to both the S and R inputs of your other load latch. Then we must measure the performance of your first latch and just use the other two copies as loads. You must also use a separate DC source for the VDD of each latch (this will ensure that you only measure the current of the first latch when calculating power and energy performance).


i) Measure and record the rise-time of output Q (from 10% to 90% of VDD) and propagation delay (from S to Q) for the set operation. Also measure and record the fall-time of output Q (from 90% to 10% of VDD) and propagation delay (from R to Q) for the reset operation. I recommend using CosmosScope to make these measurements.

ii) Measure and record the average current required (the current from the supply voltage, VDD) during your SR-Latch’s (1) hold operation, (2) set operation, and (3) reset operation (again, I recommend using CosmosScope to make these measurements). Calculate the average power dissipated during your SR-Latch’s (1) hold operation, (2) set operation, and (3) reset operation. Also calculate the average energy dissipated during your SR-Latch’s (2) set operation and (3) reset operation.

iii) Obtain waveform of your inputs (S and R) and outputs (Q and QN) showing you first asserting set and reset at the same time, and afterwards, immediately performing the hold operation. Describe what behavior you are observing and why this is occurring.

Note: >Now resize your transistors (change the NMOS and/or PMOS widths) to obtain equal rise- and fall-times. Do this in your Spice subcircuit (to ensure that all of your latches (the SR-Latch being measured and the two load latches) are still identical). Now obtain the following information from the FO4 simulation of your resized SR-Latch.

iv) List and explain the widths you chose for each of your transistors

For example: what calculations did you perform, what was the sequence of changes/simulations you performed which led you to your final transistor values, etc.
v) Compare and explain these results with your initial, minimum-sized SR-Latch
For example: how did the delays change (what percent increases/decreases and why?), how did the powers change (what percent increases/decreases and why?), etc.

Sample Answer

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